About
Hi! I'm Yu-Hsuan Li, an undergraduate student majoring in Computer Science at National Yang Ming Chiao Tung University (NYCU).
Currently, I am a research assistant at the Computational Photography Lab, proudly advised by Prof. Yu-Lun Liu.
My research interests lie in Computer Vision (CV) and Video Diffusion Models (VDM). I am highly motivated to explore video generation and its intersection with world models.
Experience
- Designed and implemented full-stack web applications utilizing React and AG Grid for robust data visualization.
- Developed efficient backend APIs using FastAPI and optimized data processing pipelines to handle large-scale data.
- Automated web scraping and data ingestion workflows using scheduled cron jobs for reliable database storage.
News
- Apr 2026 Awarded Academic Excellence Award for Fall 2025 Semester — Top 5% in class.
- Apr 2026 Awarded Core Fundamental Course Award in Introduction to Operating Systems — 2nd place out of 195 students.
- Nov 2025 Awarded Academic Excellence Award for Spring 2025 Semester — Top 5% in class.
- Nov 2025 Awarded Core Fundamental Course Award in Computer Organization — 2nd place out of 79 students.
- Sep 2025 Started internship at TSMC.
- Apr 2025 Awarded Academic Excellence Award for Fall 2024 Semester — Top 5% in class.
- Nov 2024 Awarded University Calculus Award for 2024 Spring Semester — Top 20 among all 1,162 students.
- Nov 2024 Awarded Core Fundamental Course Award in Data Structures & Object-oriented Programming — 1st place out of 90 students.
- Apr 2024 Awarded Academic Excellence Award for Fall 2023 Semester — Top 5% in class.
- Sep 2023 Enrolled as an undergraduate at National Yang Ming Chiao Tung University.
Projects
NYCU Deep Learning Labs
- 7 labs for NYCU Deep Learning & Practice course — scored 97/100 and 96/100
- Semantic segmentation (U-Net), image inpainting (MaskGIT), video prediction (VAE)
- Conditional image generation (DDPM) and reinforcement learning (DQN, PPO, A2C)
Teaching
Computer Organization (CS10014)
Teaching Assistant · National Yang Ming Chiao Tung University
Responsible for designing and grading Labs 3 – 5:
- Lab 3 Single-Cycle CPU — implement a complete RISC-V single-cycle processor in Verilog supporting 20 instructions (arithmetic, memory, branch, jump)
- Lab 4 Pipelined CPU — extend Lab 3 into a 5-stage pipeline with a Hazard Detection Unit (stall on load-use) and a Forwarding Unit (resolve data hazards)
- Lab 5 Cache Manager — implement a 2-way set-associative cache (1 KB, 16-byte blocks, LRU, Write Allocate) in C++ with correct miss-count tracking
Contact
Feel free to reach out — I'm always happy to chat about research and collaboration.
johnnyli122022@gmail.comI'm open to research collaborations, internship opportunities, and interesting conversations.